1. Field of the Invention
The present invention relates to a process for forming the field isolation structure and the gate structure of integrated MISFET devices on a monolithic semiconducting substrate. The new process is particularly suited for making devices with a high packing density (VLSI and ULSI), i.e. characterized by submicrometric features.
2. Description of the Prior Art
In MISFET devices or more specifically in integrated MOSFET devices, it is essential to provide an isolation structure among distinct integrated devices (i.e. among the active areas). A primary function of the isolation structure is that of preventing the operation of parasitic MOSFET transistors which are created by connecting together the individual real transistors. This is schematically shown in FIGS. 1 and 2, which represent respectively a schematic plan view and a partial elevation cross section of a pair of integrated MOSFET transistors: A and B, having a common gate structure constituted by the polycrystalline silicon line 1, which crosses the active areas of the two transistors A and B, between the respective source areas 2a and 2b and drain areas 3a and 3b. The two active areas are geometrically defined by the field isolation structure 4, which is constituted by a relatively thick dielectric layer, typically a field oxide layer, thermally grown by oxidation of the silicon substrate. As it is easily observed in FIGS. 1 and 2, in the zone defined by the dash-line perimeter P of FIG. 1, a parasitic MOSFET transistor is present, the gate 1 of which is common to the gate of the two real transistors, as shown in the partial cross sectional view of FIG. 2, viewed on the cross section plane II--II, indicated in FIG. 1.
In order to prevent the operation of this parasitic MOSFET it is necessary to depress as much as possible its electrical characteristics and such a function is provided by the field oxide 4, which actually represents the gate oxide of such a parasitic transistor. Usually a parameter, called threshold voltage (Vt) is defined to represent the minimum voltage which must be applied to the gate of a transistor (parasitic) for allowing a current through the transistor's channel. This critical voltage is as higher as thicker is the isolation field oxide and as higher is the doping level of the semiconducting substrate in the region underneath the isolation field oxide. For this reason, as shown in FIG. 2, the formation of the field isolation structure normally comprises the implantation of a dopant in order to create a region 5 having an increased doping level in the substrate semiconductor directly under the field oxide. Moreover the relatively thick dielectric layer constituted by the field oxide reduces the parasitic capacitance between superimposed conducting layers and the semiconducting substrate.
Conventionally the field oxide is grown by thermal oxidation of a monocrystalline silicon substrate, continued until the desired thickness of oxide is obtained over areas geometrically defined by a masking layer of silicon nitride, a material which is impervious to oxygen diffusion and which thus protects the active areas during such a heavy oxidation heat treatment, which generally requires exposing the silicon to an oxidizing atmosphere under conditions which cause oxygen to react continuously with hydrogen. Typically the field oxide thickness is greater than 5.000 Angstroms (.ANG.), i.e. at least about twenty times thicker than the gate oxide layer which normally is formed in active areas, by thermal oxidation of the silicon under strictly controlled conditions.
The growth of the field oxide for obvious reasons of productivity must be conducted at a relatively high temperature (T&gt;800.degree. C.). The masking silicon nitride has a thermal expansion coefficient substantially different from that of monocrystalline silicon and this difference of thermal expansion coefficients induces stresses in the silicon substrate which may often generate crystal lattice defects which severely affect the electrical behaviour of the integrated device. Moreover the different thermal expansion between the substrate and the masking silicon nitride layer contributes to the formation of a tapered appendix on the flank of the field oxide (also known as "planox beak"), because the oxide tends to grow, at a progressively lower rate, also under the perimetral portion of the masking nitride layer through a normal diffusion of oxygen in silicon and because the edge of the nitride layer tends to curl by rising slightly as a consequence of the difference of thermal expansion coefficient. These phenomena severely limit the possibility of reducing the dimensions of the integrated structures.
Also the remarkable loss of planarity of the front surface of the device, due to the non-negligeable height of the steps between the active areas and the top surface of the field oxide becomes an extremely limiting factor in terms of reduction of size of the integrated devices because of increasing difficulty of ensuring a good step-coverage by the metal layers to be deposited thereon (i.e. problems of electrical continuity of interconnection metal tracks).
For overcoming these limitations in order to reach higher packing densities, alternative techniques have been proposed for forming the field isolation structure, which require a pre-etching of the silicon in the isolation areas, followed by implantation of the dopant for increasing the doping level in these isolation areas, followed by filling of these etched regions with a dielectric material, e.g. a deposited silicon oxide. These techniques, also known by the acronym BOX-isolation, from "Buried Oxide Isolation", permit to maintain the surface of the front of the wafer substantially flat, but are costly because of the necessary pre-etching of the monocrystalline silicon substrate and moreover the techniques used for etching the substrate may also generate defects in the crystal.